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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14016B Quad Analog Switch/Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each MC14016B consists of four independent switches capable of controlling either digital or analog signals. The quad bilateral switch is used in signal gating, chopper, modulator, demodulator and CMOS logic implementation. * * * * * Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise -- 12 nV/Cycle, f 1.0 kHz typical Pin-for-Pin Replacements for CD4016B, CD4066B (Note improved transfer characteristic design causes more parasitic coupling capacitance than CD4016) * For Lower RON, Use The HC4016 High-Speed CMOS Device or The MC14066B * This Device Has Inputs and Outputs Which Do Not Have ESD Protection. Antistatic Precautions Must Be Taken. MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter VDD Vin, Vout lin Isw PD DC Supply Voltage L SUFFIX CERAMIC CASE 632
P SUFFIX PLASTIC CASE 646
D SUFFIX SOIC CASE 751A
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III III I I I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
Value Unit V V - 0.5 to + 18.0 10 Input or Output Voltage (DC or Transient) Input Current (DC or Transient), per Control Pin Switch Through Current Storage Temperature - 0.5 to VDD + 0.5 mA mA 25 Power Dissipation, per Package 500 260 mW Tstg TL - 65 to + 150
TA = - 55 to 125C for all packages.
BLOCK DIAGRAM
CONTROL 1 IN 1 CONTROL 2 IN 2 CONTROL 3 IN 3 CONTROL 4 IN 4 13 2 1 5 3 4 6 9 8 12 10 11 VDD = PIN 14 VSS = PIN 7 OUT 4 OUT 3 OUT 2 OUT 1
_C _C
Lead Temperature (8-Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
Control 0 = VSS 1 = VDD
Switch Off On
LOGIC DIAGRAM (1/4 OF DEVICE SHOWN)
OUT CONTROL LOGIC DIAGRAM RESTRICTIONS VSS Vin VDD VSS Vout VDD
REV 3 1/94
IN
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14016B 65
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Input/Output Leakage Current (VC = VSS) (Vin = + 7.5, Vout = - 7.5 Vdc) (Vin = - 7.5, Vout = + 7.5 Vdc) "ON" Resistance Between any 2 circuits in a common package (VC = VDD) (Vin = 5.0 Vdc, VSS = - 5.0 Vdc) (Vin = 7.5 Vdc, VSS = - 7.5 Vdc) "ON" Resistance (VC = VDD, RL = 10 k) (Vin = + 5.0 Vdc) (Vin = - 5.0 Vdc) VSS = - 5.0 Vdc (Vin = 0.25 Vdc) Quiescent Current (Per Package) Input Capacitance Control Switch Input Switch Output Feed Through Input Current Control Input Voltage Control Input (Vin = + 7.5 Vdc) (Vin = - 7.5 Vdc) VSS = - 7.5 Vdc (Vin = 0.25 Vdc) (Vin = + 10 Vdc) (Vin = + 0.25 Vdc) VSS = 0 Vdc (Vin = + 5.6 Vdc) (Vin = + 15 Vdc) (Vin = + 0.25 Vdc) VSS = 0 Vdc (Vin = + 9.3 Vdc) Characteristic Figure 4,5,6 2,3 -- -- -- -- 1 Symbol RON RON IDD VIH Cin VIL Iin -- VDD Vdc 7.5 7.5 5.0 7.5 7.5 5.0 5.0 10 15 5.0 10 15 5.0 10 15 15 10 15 -- -- -- -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.1 0.1 0.25 0.5 1.0 Max 360 360 360 600 600 600 360 360 360 600 600 600 -- -- -- -- -- -- -- -- -- -- -- -- Min 3.0 8.0 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.00001 0.0015 0.0015 0.0005 0.0010 0.0015 Typ # 25_C 260 260 300 260 310 310 240 240 180 300 300 280 5.0 5.0 5.0 0.2 2.0 6.0 11 1.5 1.5 1.5 15 10 0.1 0.1 0.1 0.25 0.5 1.0 Max 400 400 400 660 660 660 400 400 400 660 660 660 0.9 0.9 0.9 -- -- -- -- -- -- -- -- -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 1.0 1.0 Max 520 520 520 840 840 840 520 520 520 840 840 840 7.5 15 30 -- -- -- -- -- -- -- -- -- -- -- -- Ohms Ohms Adc Adc Adc Unit Vdc Vdc pF
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** For voltage drops across the switch (V switch) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e., the current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
MC14016B 66
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
OFF Channel Feedthrough Attenuation (VSS = - 5.0 Vdc) Vout -50 dB) (VC = VSS, 20 log10 Vin (RL = 1.0 k) (RL = 10 k) (RL = 100 k) (RL = 1.0 M)
Bandwidth (- 3.0 dB) (VC = VDD, Vin = 1.77 Vdc, VSS = - 5.0 Vdc, RMS centered @ 0.0 Vdc) (RL = 1.0 k) (RL = 10 k) (RL = 100 k) (RL = 1.0 M)
Insertion Loss (VC = VDD, Vin = 1.77 Vdc, VSS = - 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz) V Iloss 20 log10 out) Vin (RL = 1.0 k) (RL = 10 k) (RL = 100 k) (RL = 1.0 M)
Second Harmonic Distortion (VSS = - 5.0 Vdc) (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 k, f = 1.0 kHz)
Noise Voltage (VSS = 0 Vdc) (VC = VDD, f = 100 Hz)
Crosstalk between any two switches (VSS = 0 Vdc) (RL = 1.0 k, f = 1.0 MHz, V crosstalk 20 log10 out1) Vout2
Crosstalk, Control to Output (VSS = 0 Vdc) (VC = VDD, Rin = 10 k, Rout = 10 k, f = 1.0 kHz)
Control to Output (Vin 10 Vdc, RL = 10 k)
Propagation Delay Time (VSS = 0 Vdc) Vin to Vout (VC = VDD, RL = 10 k)
MOTOROLA CMOS LOGIC DATA
(VC = VDD, f = 100 kHz)
v
+
+
Characteristic
+
CONTROL 3
CONTROL 2
OUT 2
OUT 1
VSS
IN 1
IN 2
PIN ASSIGNMENT
Figure
7
6
5
4
3
2
1
12,13
10,11
12
--
--
--
9
8
7
Symbol
10
12
13
14
11
tPHZ, tPLZ, tPZH, tPZL
tPLH, tPHL
8
9
BW
--
--
--
--
--
--
IN 3
OUT 3
OUT 4
IN 4
CONTROL 4
CONTROL 1
VDD
VDD Vdc
5.0
5.0
5.0
5.0
5.0 10 15
5.0 10 15
5.0
5.0 10 15
5.0 10 15
5.0 10 15
Min
-- -- -- --
-- -- -- --
-- -- -- --
--
-- -- --
-- -- --
--
-- -- --
-- -- --
-- -- --
Typ #
1250 140 18 2.0
2.3 0.2 0.1 0.05
0.16
- 80
30 50 100
15 7.0 6.0
54 40 38 37
12 12 15
24 25 30
34 20 15
Max
90 45 35
45 15 12
-- -- -- --
-- -- -- --
-- -- -- --
--
-- -- --
-- -- --
--
-- -- --
MC14016B 67
nV/Cycle MHz Unit kHz mV dB dB ns ns %
VC Vin
IS Vout
VIL: VC is raised from VSS until VC = VIL. VIL: at VC = VIL: IS = 10 A with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS. VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
10,000 VDD = 15 Vdc PD , POWER DISSIPATION (W) VDD TA = 25C 1000 10 Vdc 5.0 Vdc
ID VDD Vout CONTROL INPUT VSS PD = VDD x ID Vin 10 k
100
PULSE GENERATOR
TO ALL 4 CIRCUITS fc
10
1.0 5.0 k 10 k
100 k 1.0 M fc, FREQUENCY (Hz)
10 M
50 M
Figure 2. Quiescent Power Dissipation Test Circuit
Figure 3. Typical Power Dissipation per Circuit (1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE
700 R ON, "ON" RESISTANCE (OHMS) R ON, "ON" RESISTANCE (OHMS) 600 500 400 300 200 100 0 - 10 - 8.0 VC = VDD = 7.5 Vdc VSS = - 7.5 Vdc VC = VDD = 5.0 Vdc VSS = - 5.0 Vdc RL = 10 k TA = 25C 700 600 500 400 300 200 100 0 - 4.0 0 4.0 Vin, INPUT VOLTAGE (Vdc) 8.0 10 0 2.0 6.0 10 14 Vin, INPUT VOLTAGE (Vdc) 18 20 VC = VDD = 15 Vdc VC = VDD = 10 Vdc VSS = 0 Vdc RL = 10 k TA = 25C
Figure 4. VSS = - 5.0 V and - 7.5 V
Figure 5. VSS = 0 V
MC14016B 68
MOTOROLA CMOS LOGIC DATA
Vout RL Vin Vout RL VC Vin tPLH Vin Vout 20 ns 90% 50% tPHL 50% 20 ns VDD 10% VSS CL
Figure 6. RON Characteristics Test Circuit
Figure 7. Propagation Delay Test Circuit and Waveforms
Vout VC Vin 20 ns VC tPZH Vout Vout 10% tPZL 90% 10% 50% 90% 10% VDD VC Vin 1k Vin = VSS Vx = VDD Vout 10 k 15 pF RL VX CL
VSS tPHZ Vin = VDD 90% Vx = VSS tPLZ
Figure 8. Turn-On Delay Time Test Circuit and Waveforms
Figure 9. Crosstalk Test Circuit
35 30 NOISE VOLTAGE (nV/ CYCLE) 25 10 Vdc 20 15 10 5.0 0 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 5.0 Vdc VDD = 15 Vdc
OUT VC = VDD IN
QUAN-TECH MODEL 2283 OR EQUIV
Figure 10. Noise Voltage Test Circuit
Figure 11. Typical Noise Characteristics
MOTOROLA CMOS LOGIC DATA
MC14016B 69
2.0 RL = 1 M AND 100 k TYPICAL INSERTION LOSS (dB) 0 10 k - 2.0 1.0 k - 4.0 - 6.0 - 8.0 - 10 - 12 10 k Vin 100 k 1.0 M 10 M fin, INPUT FREQUENCY (Hz) 100 M - 3.0 dB (RL = 1.0 M ) - 3.0 dB (RL = 10 k ) - 3.0 dB (RL = 1.0 k ) VC Vout RL
+ 2.5 Vdc 0.0 Vdc - 2.5 Vdc
Figure 12. Typical Insertion Loss/Bandwidth Characteristics
Figure 13. Frequency Response Test Circuit
ON SWITCH CONTROL SECTION OF IC LOAD V
SOURCE
Figure 14. V Across Switch
MC14016B 70
MOTOROLA CMOS LOGIC DATA
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0-to-5 V Digital Control signal is used to directly control a 5 V p-p analog signal. The digital control logic levels are determined by V DD and V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V logic high at the control inputs; VSS = GND = 0 V logic low. The maximum analog signal level is determined by VDD and V SS. The analog voltage must not swing higher than V DD or lower than VSS. The example shows a 5 V p-p signal which allows no margin at either peak. If voltage transients above V DD and/or below V SS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and VSS is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between V DD and V SS.
+5 V
VDD +5 V 5 Vp-p ANALOG SIGNAL SWITCH IN
VSS
+ 5.0 V
SWITCH OUT
5 Vp-p ANALOG SIGNAL
+ 2.5 V
EXTERNAL CMOS DIGITAL CIRCUITRY
0-TO-5 V DIGITAL CONTROL SIGNALS MC14016B
GND
Figure A. Application Example
VDD Dx SWITCH IN Dx SWITCH OUT
VDD Dx
Dx
VSS
VSS
Figure B. External Germanium or Schottky Clipping Diodes
MOTOROLA CMOS LOGIC DATA
MC14016B 71
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01
-A-
14 9
-B-
1 7
C
L
-T-
SEATING PLANE
K F D
14 PL
G 0.25 (0.010)
M
N J TA
S 14 PL
M 0.25 (0.010)
M
TB
S
DIM A B C D F G J K L M N
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
MC14016B 72
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA CMOS LOGIC DATA
*MC14016B/D*
MC14016B MC14016B/D 73

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